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coreboot试用

2012年6月21日 发表评论 阅读评论 20,782 次浏览

为了更深入的了解系统启动过程,想看一下bios代码,Google关键字“bios open source”,找到OpenBIOS(www.openbios.org)和coreboot(www.coreboot.org),貌似coreboot更被看好,所以就先试试它。照着官网的HOWTO文档(http://www.coreboot.org/Build_HOWTO)进行操作,首先是下载源码:

# git clone http://review.coreboot.org/p/coreboot
warning: templates not found /usr/local/share/git-core/templates
Initialized empty Git repository in /home/gqk/coreboot/.git/
Cannot get remote repository information.
Perhaps git-update-server-info needs to be run there?
# 

下载不了?换个更新版本的git下载源码成功:

[root@localhost t]# git clone http://review.coreboot.org/p/coreboot
Cloning into coreboot...
remote: Counting objects: 113272, done
remote: Finding sources: 100% (113272/113272)
remote: Total 113272 (delta 84772), reused 110776 (delta 84772)
Receiving objects: 100% (113272/113272), 28.37 MiB | 1008 KiB/s, done.
Resolving deltas: 100% (84772/84772), done.
[root@localhost t]# 

编译选项就选择采用QEMU:

[root@localhost t]# cd coreboot/
[root@localhost coreboot]# make menuconfig
[root@localhost coreboot]# make

make编译出现一大堆错误,因为是CentOS release 5.4,估计是编译环境版本太低,换到CentOS Linux release 6.0:

[root@localhost coreboot]# make
...
    CC         devices/pci_rom.ramstage.o
gcc: -b: linker input file unused because linking not done
gcc: elf32-i386: linker input file unused because linking not done
gcc: -melf_i386: linker input file unused because linking not done
gcc: --build-id=none: linker input file unused because linking not done
...
  Compiling whole program /home/t/coreboot/build/seabios/out/ccode16.o
src/pmm.c: In function 'handle_pmm':
src/pmm.c:569: warning: case label value exceeds maximum value for type
src/output.c: In function 'bvprintf':
src/output.c:325: warning: case label value exceeds maximum value for type
...
gcc: --build-id=none: linker input file unused because linking not done
  Generating offset file /home/t/coreboot/build/seabios/out/asm-offsets.h
  Compiling (16bit) /home/t/coreboot/build/seabios/out/romlayout.o
gcc: -b: linker input file unused because linking not done
gcc: elf32-i386: linker input file unused because linking not done
gcc: -melf_i386: linker input file unused because linking not done
gcc: --build-id=none: linker input file unused because linking not done
...
[root@localhost coreboot]# cat /etc/issue
CentOS release 5.4 (Final)
Kernel \r on an \m

->

[root@localhost ~]# cat /etc/issue
CentOS Linux release 6.0 (Final)
Kernel \r on an \m

[root@localhost ~]# uname -a
Linux localhost.localdomain 2.6.38.8 #5 SMP Sun May 27 13:43:35 CST 2012 x86_64 x86_64 x86_64 GNU/Linux
[root@localhost ~]# 

编译成功,生成rom文件:

[root@localhost coreboot]# make
    GEN        build.h
    ROMCC      romstage.inc
    GEN        generated/crt0.romstage.S
    CC         generated/crt0.s
    CC         generated/crt0.romstage.o
    CC         generated/bootblock.s
    CC         generated/bootblock.o
    LINK       cbfs/fallback/bootblock.debug
    OBJCOPY    cbfs/fallback/bootblock.elf
    OBJCOPY    cbfs/fallback/bootblock.bin
    LINK       cbfs/fallback/romstage_null.debug
    OBJCOPY    cbfs/fallback/romstage_null.elf
    OBJCOPY    cbfs/fallback/romstage_null.bin
    GEN        generated/romstage_xip.ld
    LINK       cbfs/fallback/romstage_xip.debug
    OBJCOPY    cbfs/fallback/romstage_xip.elf
    CBFS       coreboot.pre
    CC         arch/x86/boot/smbios.ramstage.o
    CC         console/console.ramstage.o
    CC         lib/version.ramstage.o
    AR         generated/ramstage.a
    CC         generated/coreboot_ram.o
    CC         cbfs/fallback/coreboot_ram.debug
    OBJCOPY    cbfs/fallback/coreboot_ram.elf
    Checking out SeaBIOS revision a0263083cb4cda172832fbc916dc1417ee930574
Switched to branch 'master'
Deleted branch coreboot (was a026308).
Switched to a new branch 'coreboot'
    CONFIG     SeaBIOS a0263083cb4cda172832fbc916dc1417ee930574
  Build default config
#
# configuration written to /home/coreboot/build/seabios/.config
#
    MAKE       SeaBIOS a0263083cb4cda172832fbc916dc1417ee930574
  Build Kconfig config file
/home/coreboot/build/seabios/.config:89:warning: override: reassigning to symbol COREBOOT
/home/coreboot/build/seabios/.config:90:warning: override: reassigning to symbol DEBUG_SERIAL
/home/coreboot/build/seabios/.config:95:warning: override: reassigning to symbol VGAHOOKS
#
# configuration written to /home/coreboot/build/seabios/.config
#
  Compiling whole program /home/coreboot/build/seabios/out/ccode32flat.o
  Compiling whole program /home/coreboot/build/seabios/out/code32seg.o
  Compiling whole program /home/coreboot/build/seabios/out/ccode16.o
  Compiling to assembler /home/coreboot/build/seabios/out/asm-offsets.s
  Generating offset file /home/coreboot/build/seabios/out/asm-offsets.h
  Compiling (16bit) /home/coreboot/build/seabios/out/romlayout.o
  Building ld scripts
Version: rel-1.7.0-0-ga026308-20121212_033029-localhost.localdomain
Fixed space: 0xe05b-0x10000  total: 8101  slack: 9  Percent slack: 0.1%
16bit size:           41680
32bit segmented size: 2295
32bit flat size:      16297
32bit flat init size: 44288
  Linking /home/coreboot/build/seabios/out/rom16.o
  Stripping /home/coreboot/build/seabios/out/rom16.strip.o
  Linking /home/coreboot/build/seabios/out/rom32seg.o
  Stripping /home/coreboot/build/seabios/out/rom32seg.strip.o
  Linking /home/coreboot/build/seabios/out/rom.o
  Prepping /home/coreboot/build/seabios/out/bios.bin
Total size: 106644  Fixed: 60276  Free: 24428 (used 81.4% of 128KiB rom)
    CBFS       coreboot.rom
    PAYLOAD    SeaBIOS (internal, compression: LZMA)
    CONFIG     .config
    CBFSPRINT  coreboot.rom

coreboot.rom: 256 kB, bootblocksize 848, romsize 262144, offset 0x0
Alignment: 64 bytes

Name                           Offset     Type         Size
cmos_layout.bin                0x0        cmos layout  1160
fallback/romstage              0x4c0      stage        9157
fallback/coreboot_ram          0x28c0     stage        29122
fallback/payload               0x9ac0     payload      53433
config                         0x16bc0    raw          2433
(empty)                        0x17580    null         165608
[root@localhost coreboot]# cd build/
[root@localhost build]# pwd
/home/coreboot/build
[root@localhost build]# ls coreboot.rom -l
-rw-r--r--. 1 root root 262144 Dec 12 00:52 coreboot.rom
[root@localhost build]# 

再参照官网帮助文档(http://www.coreboot.org/QEMU_Build_Tutorial)进行qemu试用,我这里只关心bios执行过程,所以无需准备FILO或Linux内核镜像。从http://sourceforge.net/projects/kvm/files/qemu-kvm/下载qemu,解压安装(./configure; make; make install)后,执行:

[root@localhost qemu-kvm-1.0.1]# qemu-system-x86_64 -no-kvm -nographic -bios /home/coreboot/build/coreboot.rom


coreboot-4.0-2469-g1454685-dirty Wed Dec 12 00:51:53 CST 2012 starting...
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (114688 bytes), entry @ 0x100000
Jumping to image.
coreboot-4.0-2469-g1454685-dirty Wed Dec 12 00:51:53 CST 2012 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
Compare with tree...
Root Device: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:01.1: enabled 1
scan_static_bus for Root Device
Finding PCI configuration type.
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/1237] ops
PCI: 00:00.0 [8086/1237] enabled
PCI: 00:01.0 [8086/7000] bus ops
PCI: 00:01.0 [8086/7000] enabled
PCI: 00:01.1 [8086/7010] ops
PCI: 00:01.1 [8086/7010] enabled
PCI: 00:01.3 [8086/7113] bus ops
pwrmgt_enable: gpo default missing in devicetree.cb!
PCI: 00:01.3 [8086/7113] enabled
PCI: 00:02.0 [1013/00b8] ops
PCI: 00:02.0 [1013/00b8] enabled
PCI: 00:03.0 [10ec/8139] enabled
scan_static_bus for PCI: 00:01.0
scan_static_bus for PCI: 00:01.0 done
scan_static_bus for PCI: 00:01.3
scan_static_bus for PCI: 00:01.3 done
PCI: pci_scan_bus returning with max=000
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 PCI_DOMAIN: 0000
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2
  PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
   PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
   PCI: 00:01.1
   PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:01.3
   PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
   PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
   PCI: 00:02.0
   PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10
   PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
   PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
   PCI: 00:03.0
   PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
   PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14
   PCI: 00:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:03.0 10 *  [0x0 - 0xff] io
PCI: 00:01.1 20 *  [0x400 - 0x40f] io
PCI_DOMAIN: 0000 compute_resources_io: base: 410 size: 410 align: 8 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:02.0 10 *  [0x0 - 0x1ffffff] prefmem
PCI: 00:02.0 30 *  [0x2000000 - 0x200ffff] mem
PCI: 00:03.0 30 *  [0x2010000 - 0x201ffff] mem
PCI: 00:02.0 14 *  [0x2020000 - 0x2020fff] mem
PCI: 00:03.0 14 *  [0x2021000 - 0x20210ff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 2021100 size: 2021100 align: 25 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:01.1
constrain_resources: PCI: 00:01.3
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:03.0
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000e3ff
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
	lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:410 align:8 gran:0 limit:e3ff
Assigned: PCI: 00:03.0 10 *  [0x1000 - 0x10ff] io
Assigned: PCI: 00:01.1 20 *  [0x1400 - 0x140f] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1410 size: 410 align: 8 gran: 0 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2021100 align:25 gran:0 limit:febfffff
Assigned: PCI: 00:02.0 10 *  [0xfc000000 - 0xfdffffff] prefmem
Assigned: PCI: 00:02.0 30 *  [0xfe000000 - 0xfe00ffff] mem
Assigned: PCI: 00:03.0 30 *  [0xfe010000 - 0xfe01ffff] mem
Assigned: PCI: 00:02.0 14 *  [0xfe020000 - 0xfe020fff] mem
Assigned: PCI: 00:03.0 14 *  [0xfe021000 - 0xfe0210ff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe021100 size: 2021100 align: 25 gran: 0 done
Root Device assign_resources, bus 0 link: 0
Detected 131072 Kbytes (128 MiB) RAM.
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io
PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem
PCI: 00:02.0 14 <- [0x00fe020000 - 0x00fe020fff] size 0x00001000 gran 0x0c mem
PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 romem
PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:03.0 14 <- [0x00fe021000 - 0x00fe0210ff] size 0x00000100 gran 0x08 mem
PCI: 00:03.0 30 <- [0x00fe010000 - 0x00fe01ffff] size 0x00010000 gran 0x10 romem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 PCI_DOMAIN: 0000
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit e3ff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base fc000000 size 2021100 align 25 gran 0 limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2
  PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
  PCI_DOMAIN: 0000 resource base c0000 size 7f40000 align 0 gran 0 limit 0 flags e0004200 index b
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
   PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
   PCI: 00:01.1
   PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20
   PCI: 00:01.3
   PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
   PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
   PCI: 00:02.0
   PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit febfffff flags 60001200 index 10
   PCI: 00:02.0 resource base fe020000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14
   PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30
   PCI: 00:03.0
   PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10
   PCI: 00:03.0 resource base fe021000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14
   PCI: 00:03.0 resource base fe010000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 00
PCI: 00:01.0 cmd <- 00
PCI: 00:01.1 cmd <- 01
PCI: 00:01.3 cmd <- 00
PCI: 00:02.0 cmd <- 03
PCI: 00:03.0 cmd <- 03
done.
Initializing devices...
Root Device init
PCI: 00:00.0 init
Keyboard init...
setting ethernet
Assigning IRQ 11 to 0:3.0
i8259_configure_irq_trigger: current interrupts are 0x0
i8259_configure_irq_trigger: try to set interrupts 0x800
PCI: 00:01.0 init
RTC Init
PCI: 00:01.1 init
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: off
PCI: 00:02.0 init
CBFS: Looking for 'pci1013,00b8.rom'
CBFS: Could not find file 'pci1013,00b8.rom'.
Option ROM address for PCI: 00:02.0 = fe000000
PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x010f
PCI ROM image, vendor ID 1013, device ID 00b8,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...
... Option ROM returned.
PCI: 00:03.0 init
CBFS: Looking for 'pci10ec,8139.rom'
CBFS: Could not find file 'pci10ec,8139.rom'.
Option ROM address for PCI: 00:03.0 = fe010000
PCI expansion ROM, signature 0xaa55, INIT size 0xf000, data ptr 0x0020
PCI ROM image, vendor ID 10ec, device ID 8139,
PCI ROM image, Class Code 000002, Code Type 00
Class Code mismatch ROM 00000002, dev 00020000
Copying non-VGA ROM image from fe010000 to 000d0000, 0xf000 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...

iPXE v1.0.0-591-g7aee315
iPXE (http://ipxe.org) 00:03.0 D000 INT19 D000
                                                                               

... Option ROM returned.
Devices initialized
Show all devs...After init.
Root Device: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:01.3: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
Re-Initializing CBMEM area to 0x7fe0000
Initializing CBMEM area to 0x7fe0000 (131072 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 07fe0200...ok
High Tables Base is 7fe0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x07fe0400... done.
PIRQ table: 128 bytes.
Adding CBMEM entry as no. 3
smbios_write_tables: 07fe1400
Root Device (QEMU Mainboard)
PCI_DOMAIN: 0000 (QEMU Northbridge)
PCI: 00:00.0 (QEMU Northbridge)
PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:01.3 ()
PCI: 00:02.0 ()
PCI: 00:03.0 ()
SMBIOS tables: 376 bytes.
Adding CBMEM entry as no. 4
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum dbe0
New low_table_end: 0x00000528
Now going to write high coreboot table at 0x07fe1c00
rom_table_end = 0x07fe1c00
Adjust low_table_end from 0x00000528 to 0x00001000 
Adjust rom_table_end from 0x07fe1c00 to 0x07ff0000 
Adding high table area
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-0000000007fdffff: RAM
 3. 0000000007fe0000-0000000007ffffff: CONFIGURATION TABLES
 4. 00000000ff800000-00000000ffffffff: RESERVED
Wrote coreboot table at: 07fe1c00, 0x1f4 bytes, checksum 2e45
coreboot table: 524 bytes.
Multiboot Information structure has been written.
 0. FREE SPACE 07fe9c00 00016400
 1. GDT        07fe0200 00000200
 2. IRQ TABLE  07fe0400 00001000
 3. SMBIOS     07fe1400 00000800
 4. COREBOOT   07fe1c00 00008000
CBFS: Looking for 'fallback/payload'
CBFS: found.
Got a payload
Loading segment from rom address 0xfffc9af8
  code (compression=1)
  New segment dstaddr 0xe5f6c memsize 0x1a094 srcaddr 0xfffc9b30 filesize 0xd081
  (cleaned up) New segment addr 0xe5f6c size 0x1a094 offset 0xfffc9b30 filesize 0xd081
Loading segment from rom address 0xfffc9b14
  Entry Point 0x00000000
Loading Segment: addr: 0x00000000000e5f6c memsz: 0x000000000001a094 filesz: 0x000000000000d081
lb: [0x0000000000100000, 0x000000000011c000)
Post relocation: addr: 0x00000000000e5f6c memsz: 0x000000000001a094 filesz: 0x000000000000d081
using LZMA
[ 0x000e5f6c, 00100000, 0x00100000) <- fffc9b30
dest 000e5f6c, end 00100000, bouncebuffer 7fa8000
Loaded segments
Jumping to boot code at fc88b
entry    = 0x000fc88b
lb_start = 0x00100000
lb_size  = 0x0001c000
adjust   = 0x07ec4000
buffer   = 0x07fa8000
     elf_boot_notes = 0x0010d62c
adjusted_boot_notes = 0x07fd162c
Start bios (version rel-1.7.0-0-ga026308-20121212_005202-localhost.localdomain)
Found mainboard Emulation QEMU x86
Found CBFS header at 0xfffffc90
Ram Size=0x07fe0000 (0x0000000000000000 high)
Relocating init from 0x000e6790 to 0x07fc51e0 (size 44284)
CPU Mhz=2566
Found 6 PCI devices (max PCI bus is 00)
Found 1 cpu(s) max supported 1 cpu(s)
Copying PIR from 0x07fe0400 to 0x000fdae0
Copying SMBIOS entry point from 0x07fe1400 to 0x000fdac0
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.7.0-0-ga026308-20121212_005202-localhost.localdomain)

Found 1 lpt ports
Found 1 serial ports
ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9)
ATA controller 2 at 170/374/0 (irq 15 dev 9)
DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD]
Searching bootorder for: /pci@i0cf8/*@1,1/drive@1/disk@0
PS2 keyboard initialized
All threads complete.
Scan for option roms
Running option rom at c900:0003
pmm call arg1=1
pmm call arg1=0
pmm call arg1=1
pmm call arg1=0
Searching bootorder for: /pci@i0cf8/*@3
Press F12 for boot menu.

ebda moved from 9fc00 to 9f400
Returned 65536 bytes of ZoneHigh
e820 map has 6 items:
  0: 0000000000000000 - 000000000009f400 = 1 RAM
  1: 000000000009f400 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 0000000007fe0000 = 1 RAM
  4: 0000000007fe0000 - 0000000008000000 = 2 RESERVED
  5: 00000000ff800000 - 0000000100000000 = 2 RESERVED
enter handle_19:
  NULL
Booting from DVD/CD...
Device reports MEDIUM NOT PRESENT
scsi_is_ready returned -1
Boot failed: Could not read from CDROM (code 0003)
enter handle_18:
  NULL
Booting from ROM...
Booting from c900:0372
enter handle_18:
  NULL
Booting from Floppy...
Boot failed: could not read the boot disk

enter handle_18:
  NULL
Booting from Hard Disk...
Boot failed: could not read the boot disk

enter handle_18:
  NULL
No bootable device.

-no-kvm表示不启动kvm特性,其实我这台机器是一台vmware虚拟机,当然不支持kvm。
-nographic表示不要图形输出,我这里是ssh远程链接,所以要关掉,否则将提示:Could not initialize SDL(No available video device) – exiting
-bios指定我编译生成的bios程序 /home/coreboot/build/coreboot.rom

qemu执行输出很多bios,最后卡死在启动设备上,因为我没指定。

http://www.openfirmware.info/Welcome_to_OpenBIOS
http://www.fsf.org/campaigns/free-bios.html
http://www.coreboot.org/Build_HOWTO
https://luxitude.net/ubuntu/pool/main/m/mkelfimage/mkelfimage_2.7.orig.tar.gz
http://www.coreboot.org/QEMU_Build_Tutorial

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  1. peter90609
    2015年7月1日16:00 | #1

    你好!:
    我也嘗試著和你使用一樣的方式建置,不過在run qemu的時候會失敗,以下是我的Error message
    IMD small region:
    IMD ROOT 0. 07ffec00 00000400
    CAR GLOBALS 1. 07ffebe0 0000000c
    ROMSTAGE 2. 07ffebc0 00000004
    GDT 3. 07ffe9c0 00000200
    CBFS provider active.
    CBFS @ 100000 size ffc80
    CBFS: Locating ‘fallback/payload’
    CBFS: Found @ offset 102c0 size c5a5
    ‘fallback/payload’ located at offset: 1102f8 size: c5a5
    Loading segment from rom address 0xfff102f8
    code (compression=1)
    New segment dstaddr 0xe7c04 memsize 0x183fc srcaddr 0xfff10330 filesize 0xc56d
    Loading segment from rom address 0xfff10314
    Entry Point 0x000fcfff
    Bounce Buffer at 07f5e000, 338264 bytes
    Loading Segment: addr: 0x00000000000e7c04 memsz: 0x00000000000183fc filesz: 0x000000000000c56d
    lb: [0x0000000000100000, 0x00000000001294ac)
    Post relocation: addr: 0x00000000000e7c04 memsz: 0x00000000000183fc filesz: 0x000000000000c56d
    using LZMA
    lzma: Decoding error = 1
    Payload not loaded.

    如果可以的話,可以分享一下你的建置環境嗎?seabios的版本 & config 設定,非常感激!
    我的mail: peter90609@gmail.com

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